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Espressif Systems /ESP32-P4 /SPI0 /SPI_MEM_MMU_POWER_CTRL

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Interpret as SPI_MEM_MMU_POWER_CTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SPI_MMU_MEM_FORCE_ON)SPI_MMU_MEM_FORCE_ON 0 (SPI_MMU_MEM_FORCE_PD)SPI_MMU_MEM_FORCE_PD 0 (SPI_MMU_MEM_FORCE_PU)SPI_MMU_MEM_FORCE_PU 0SPI_MEM_AUX_CTRL0 (SPI_MEM_RDN_ENA)SPI_MEM_RDN_ENA 0 (SPI_MEM_RDN_RESULT)SPI_MEM_RDN_RESULT

Description

MSPI MMU power control register

Fields

SPI_MMU_MEM_FORCE_ON

Set this bit to enable mmu-memory clock force on
SPI_MMU_MEM_FORCE_PD

Set this bit to force mmu-memory powerdown
SPI_MMU_MEM_FORCE_PU

Set this bit to force mmu-memory powerup, in this case, the power should also be controlled by rtc.
SPI_MEM_AUX_CTRL

MMU PSRAM aux control register
SPI_MEM_RDN_ENA

ECO register enable bit
SPI_MEM_RDN_RESULT

MSPI module clock domain and AXI clock domain ECO register result register

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/espressif/svd